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108 lines
2.9 KiB
Verilog
108 lines
2.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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// surefire lint_off ASWEBB
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// surefire lint_off ASWEMB
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// surefire lint_off STMINI
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// surefire lint_off CSEBEQ
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input clk;
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reg [7:0] a_to_clk_levm3;
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reg [7:0] b_to_clk_levm1;
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reg [7:0] c_com_levs10;
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reg [7:0] d_to_clk_levm2;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] m_from_clk_lev1_r; // From a of t_order_a.v
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wire [7:0] n_from_clk_lev2; // From a of t_order_a.v
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wire [7:0] o_from_com_levs11; // From a of t_order_a.v
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wire [7:0] o_from_comandclk_levs12;// From a of t_order_a.v
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wire [7:0] o_subfrom_clk_lev2; // From b of t_order_b.v
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// End of automatics
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reg [7:0] cyc; initial cyc=0;
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t_order_a a (
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.one (8'h1),
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/*AUTOINST*/
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// Outputs
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.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]),
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.n_from_clk_lev2 (n_from_clk_lev2[7:0]),
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.o_from_com_levs11 (o_from_com_levs11[7:0]),
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.o_from_comandclk_levs12(o_from_comandclk_levs12[7:0]),
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// Inputs
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.clk (clk),
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.a_to_clk_levm3 (a_to_clk_levm3[7:0]),
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.b_to_clk_levm1 (b_to_clk_levm1[7:0]),
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.c_com_levs10 (c_com_levs10[7:0]),
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.d_to_clk_levm2 (d_to_clk_levm2[7:0]));
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t_order_b b (
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/*AUTOINST*/
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// Outputs
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.o_subfrom_clk_lev2 (o_subfrom_clk_lev2[7:0]),
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// Inputs
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.m_from_clk_lev1_r (m_from_clk_lev1_r[7:0]));
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reg [7:0] o_from_com_levs12;
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reg [7:0] o_from_com_levs13;
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always @ (/*AS*/o_from_com_levs11) begin
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o_from_com_levs12 = o_from_com_levs11 + 8'h1;
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o_from_com_levs12 = o_from_com_levs12 + 8'h1; // Test we can add to self and optimize
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o_from_com_levs13 = o_from_com_levs12;
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end
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reg sepassign_in;
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// verilator lint_off UNOPTFLAT
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wire [3:0] sepassign;
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// verilator lint_on UNOPTFLAT
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// verilator lint_off UNOPT
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assign #0.1 sepassign[0] = 0,
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sepassign[1] = sepassign[2],
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sepassign[2] = sepassign[3],
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sepassign[3] = sepassign_in;
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wire [7:0] o_subfrom_clk_lev3 = o_subfrom_clk_lev2;
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// verilator lint_on UNOPT
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always @ (posedge clk) begin
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cyc <= cyc+8'd1;
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sepassign_in <= 0;
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if (cyc == 8'd1) begin
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a_to_clk_levm3 <= 0;
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d_to_clk_levm2 <= 1;
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b_to_clk_levm1 <= 1;
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c_com_levs10 <= 2;
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sepassign_in <= 1;
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end
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if (cyc == 8'd2) begin
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if (sepassign !== 4'b1110) $stop;
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end
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if (cyc == 8'd3) begin
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$display("%d %d %d %d",m_from_clk_lev1_r,
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n_from_clk_lev2,
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o_from_com_levs11,
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o_from_comandclk_levs12);
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if (m_from_clk_lev1_r !== 8'h2) $stop;
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if (o_subfrom_clk_lev3 !== 8'h2) $stop;
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if (n_from_clk_lev2 !== 8'h2) $stop;
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if (o_from_com_levs11 !== 8'h3) $stop;
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if (o_from_com_levs13 !== 8'h5) $stop;
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if (o_from_comandclk_levs12 !== 8'h5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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