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60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// bug789 generates
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc #(1) itopa();
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ifc #(2) itopb();
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sub #(1) ca (.isub(itopa),
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.i_value(4));
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sub #(2) cb (.isub(itopb),
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.i_value(5));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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if (itopa.MODE != 1) $stop;
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if (itopb.MODE != 2) $stop;
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end
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if (cyc==20) begin
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if (itopa.i != 4) $stop;
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if (itopb.i != 5) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub
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#(parameter MODE = 0)
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(
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ifc isub,
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input integer i_value
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);
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// Commercial unsupported Xmrs into scopes within interfaces
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generate
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always_comb isub.i = i_value;
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endgenerate
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endmodule
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interface ifc;
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parameter MODE = 0;
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// Commercial unsupported Xmrs into scopes within interfaces
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generate
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integer i;
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endgenerate
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endinterface
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