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31 lines
586 B
Verilog
31 lines
586 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty.
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// SPDX-License-Identifier: CC0-1.0
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// bug1005
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module foo_module;
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generate
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for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block
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logic baz;
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end
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endgenerate
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endmodule
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module bar_module;
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foo_module foo();
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endmodule
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module t;
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bar_module bar();
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initial begin
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bar.foo.my_gen_block[0].baz = 1;
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if (bar.foo.my_gen_block[0].baz) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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