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95 lines
2.0 KiB
Verilog
95 lines
2.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Test:
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tri t;
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bufif1 (t, crc[1], cyc[1:0]==2'b00);
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bufif1 (t, crc[2], cyc[1:0]==2'b10);
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tri0 t0;
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bufif1 (t0, crc[1], cyc[1:0]==2'b00);
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bufif1 (t0, crc[2], cyc[1:0]==2'b10);
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tri1 t1;
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bufif1 (t1, crc[1], cyc[1:0]==2'b00);
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bufif1 (t1, crc[2], cyc[1:0]==2'b10);
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tri t2;
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t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
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bufif1 (t2, crc[2], cyc[1:0]==2'b10);
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tri t3;
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t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00));
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bufif1 (t3, crc[2], cyc[1:0]==2'b10);
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wire [63:0] result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h04f91df71371e950
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t_tri2 (/*AUTOARG*/
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// Outputs
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t2,
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// Inputs
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d, oe
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);
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output t2;
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input d;
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input oe;
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tri1 t2;
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bufif1 (t2, d, oe);
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endmodule
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module t_tri3 (/*AUTOARG*/
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// Outputs
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t3,
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// Inputs
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d, oe
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);
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output tri1 t3;
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input d;
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input oe;
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bufif1 (t3, d, oe);
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endmodule
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