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8bitworkshop/presets/verilog/skeleton.verilator
2018-02-05 18:05:49 -06:00

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`include "hvsync_generator.v"
module top(clk, reset, hsync, vsync, rgb);
input clk, reset;
output hsync, vsync;
output [2:0] rgb;
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
hvsync_generator hvsync_gen(
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
wire r = display_on && hpos[4];
wire g = display_on && vpos[4];
wire b = display_on && hpos[0];
assign rgb = {b,g,r};
endmodule