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57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This test case is used for testing a modeule parameterized with a typed
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// localparam.
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//
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// We find Verilator appears to mis-evaluate the parameter WIDTH as -16 when
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// used in the test module to set the value of MSB. A number of warnings and
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// errors follow, starting with:
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//
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// %Warning-LITENDIAN: t/t_param_module.v:42: Little bit endian vector: MSB
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// < LSB of bit range: -17:0
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//
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// This file ONLY is placed into the Public Domain, for any use, without
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// warranty, 2013 by Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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// bug606
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam logic[4:0] WID = 16;
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//localparam WID = 16; // No problem if defined like this
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wire [15:0] b33;
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test #(WID) i_test_33(.clk (clk),
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.b (b33));
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endmodule
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module test (/*AUTOARG*/
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//Inputs
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clk,
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// Outputs
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b
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);
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parameter WIDTH = 10;
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localparam MSB = WIDTH - 1;
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input clk;
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output wire [MSB:0] b;
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wire [MSB:0] a;
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assign b = {~a[MSB-1:0], clk};
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initial begin
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if ($bits(WIDTH)!=5) $stop; // Comes from the parent!
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if ($bits(MSB)!=32) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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