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65 lines
1.8 KiB
Verilog
65 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2012 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/);
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`define ASSERT(x) initial if (!(x)) $stop
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// See IEEE 6.20.2 on value parameters
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localparam unsigned [63:0] UNSIGNED =64'h99934567_89abcdef;
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localparam signed [63:0] SIGNED =64'sh99934567_89abcdef;
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localparam real REAL=1.234;
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`ASSERT(UNSIGNED > 0);
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`ASSERT(SIGNED < 0);
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// bullet 1
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localparam A1_WIDE = UNSIGNED;
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`ASSERT($bits(A1_WIDE)==64);
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localparam A2_REAL = REAL;
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`ASSERT(A2_REAL == 1.234);
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localparam A3_SIGNED = SIGNED;
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`ASSERT($bits(A3_SIGNED)==64 && A3_SIGNED < 0);
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localparam A4_EXPR = (2'b01 + 2'b10);
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`ASSERT($bits(A4_EXPR)==2 && A4_EXPR==2'b11);
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// bullet 2
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localparam [63:0] B_UNSIGNED = SIGNED;
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`ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0);
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// bullet 3
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localparam signed C_SIGNED = UNSIGNED;
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`ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0);
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localparam unsigned C_UNSIGNED = SIGNED;
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`ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0);
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// bullet 4
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// verilator lint_off WIDTH
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localparam signed [59:0] D_SIGNED = UNSIGNED;
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`ASSERT($bits(D_SIGNED)==60 && D_SIGNED < 0);
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// verilator lint_on WIDTH
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// verilator lint_off WIDTH
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localparam unsigned [59:0] D_UNSIGNED = SIGNED;
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`ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0);
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// verilator lint_on WIDTH
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// bullet 6
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localparam UNSIZED = 23;
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`ASSERT($bits(UNSIZED)>=32);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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