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49 lines
920 B
Verilog
49 lines
920 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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interface ifc;
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integer value;
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modport i (output value);
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modport o (input value);
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=1;
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ifc itop1a(),
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itop1b();
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wrapper c1 (.isuba(itop1a),
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.isubb(itop1b),
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.i_valuea(14),
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.i_valueb(15));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==20) begin
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if (itop1a.value != 14) $stop;
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if (itop1b.value != 15) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module wrapper
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(
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ifc.i isuba, isubb,
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input integer i_valuea, i_valueb
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);
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always @* begin
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isuba.value = i_valuea;
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isubb.value = i_valueb;
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end
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endmodule
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