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30 lines
557 B
Verilog
30 lines
557 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Legal with Verilog 1995 style ports
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module t
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(/*AUTOARG*/
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// Outputs
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ok_o_w, ok_o_r, ok_o_ra, ok_or, ok_ow, ok_owa
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);
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output ok_o_w;
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wire ok_o_w;
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output ok_o_r;
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reg ok_o_r;
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output [1:0] ok_o_ra;
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reg [1:0] ok_o_ra;
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output reg ok_or;
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output wire ok_ow;
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output wire [1:0] ok_owa;
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endmodule
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