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29 lines
524 B
Verilog
29 lines
524 B
Verilog
// DESCRIPTION: Verilator: Unsupported tristate construct error
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//
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// This is a compile only regression test of tristate handling for bug514
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [11:0] ck;
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assign ck[1:0] = {1'bz,{1{1'b0}}};
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test i_test (.clk (ck[1:0]));
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endmodule
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module test (clk);
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output wire [1:0] clk;
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endmodule // test
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