mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-06-07 01:29:30 +00:00
66 lines
2.8 KiB
INI
66 lines
2.8 KiB
INI
SYMBOLS {
|
|
__STACKSIZE__: type = weak, value = $0600;
|
|
}
|
|
MEMORY {
|
|
# Zero Page
|
|
ZP: file = "", start = $0040, size = $00C0, type = rw, define = yes;
|
|
|
|
# Cartridge Header
|
|
HEADER: file = %O, start = $0000, size = $0080, fill = yes;
|
|
|
|
# ROM Bank
|
|
PRG: file = %O, start = $4000, size = $4000, fill = yes, define = yes;
|
|
|
|
# DMA/Code Banks (interleaved for 4K Holey DMA)
|
|
CHR0: file = %O, start = $8000, size = $1000, fill = yes, define = yes;
|
|
PRG0: file = %O, start = $9000, size = $1000, fill = yes, define = yes;
|
|
CHR1: file = %O, start = $A000, size = $1000, fill = yes, define = yes;
|
|
PRG1: file = %O, start = $B000, size = $1000, fill = yes, define = yes;
|
|
CHR2: file = %O, start = $C000, size = $1000, fill = yes, define = yes;
|
|
PRG2: file = %O, start = $D000, size = $1000, fill = yes, define = yes;
|
|
CHR3: file = %O, start = $E000, size = $1000, fill = yes, define = yes;
|
|
PRG3: file = %O, start = $F000, size = $0FFA, fill = yes, define = yes;
|
|
|
|
# CPU Vectors
|
|
VECTORS: file = %O, start = $FFFA, size = $0006, fill = yes;
|
|
|
|
# standard 2k SRAM (-zeropage)
|
|
RAM0: file = "", start = $1800, size = $840, define = yes;
|
|
RAM1: file = "", start = $2200, size = __STACKSIZE__, define = yes;
|
|
}
|
|
SEGMENTS {
|
|
ZEROPAGE: load = ZP, type = zp;
|
|
HEADER: load = HEADER, type = ro;
|
|
STARTUP: load = PRG, type = ro, define = yes;
|
|
RODATA: load = PRG, type = ro, define = yes;
|
|
ONCE: load = PRG, type = ro, optional = yes;
|
|
CODE: load = PRG, type = ro, define = yes;
|
|
DATA: load = PRG, run = RAM0, type = rw, define = yes;
|
|
CHR0: load = CHR0, type = ro, optional = yes;
|
|
PRG0: load = PRG0, type = ro, optional = yes;
|
|
CHR1: load = CHR1, type = ro, optional = yes;
|
|
PRG1: load = PRG1, type = ro, optional = yes;
|
|
CHR2: load = CHR2, type = ro, optional = yes;
|
|
PRG2: load = PRG2, type = ro, optional = yes;
|
|
CHR3: load = CHR3, type = ro, optional = yes;
|
|
PRG3: load = PRG3, type = ro, optional = yes;
|
|
VECTORS: load = VECTORS, type = ro;
|
|
BSS: load = RAM0, type = bss, define = yes;
|
|
RAM1: load = RAM1, type = rw, optional = yes;
|
|
}
|
|
FEATURES {
|
|
CONDES: type = constructor,
|
|
label = __CONSTRUCTOR_TABLE__,
|
|
count = __CONSTRUCTOR_COUNT__,
|
|
segment = ONCE;
|
|
CONDES: type = destructor,
|
|
label = __DESTRUCTOR_TABLE__,
|
|
count = __DESTRUCTOR_COUNT__,
|
|
segment = RODATA;
|
|
CONDES: type = interruptor,
|
|
label = __INTERRUPTOR_TABLE__,
|
|
count = __INTERRUPTOR_COUNT__,
|
|
segment = RODATA,
|
|
import = __CALLIRQ__;
|
|
}
|