8bitworkshop/fpga/examples/test.vlog

module test;

reg clk;
reg reset;
reg hpaddle;
reg vpaddle;
wire out0;
wire out1;

chip chip(
 .io_7_0_0(clk),
 .io_0_8_1(reset),
 .io_13_4_0(hpaddle),
 .io_13_3_1(vpaddle),
 .io_13_6_0(out0),
 .io_13_4_1(out1)
);

always #2 clk = !clk;

initial begin
  $dumpfile("racing_game_cpu.vcd");
  $dumpvars(0,test);

  #1 clk = 0;
  #5 reset = 1;
  #10 reset = 0;

  #100000 $finish();
end

endmodule