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https://github.com/sehugg/8bitworkshop.git
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90 lines
2.4 KiB
Verilog
90 lines
2.4 KiB
Verilog
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/*
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Displays a 32x30 grid of 8x8 tiles, whose attributes are
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fetched from RAM, and whose bitmap patterns are in ROM.
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*/
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module tile_renderer(clk, reset, hpos, vpos,
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rgb,
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ram_addr, ram_read, ram_busy,
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rom_addr, rom_data);
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input clk, reset;
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input [8:0] hpos;
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input [8:0] vpos;
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output [3:0] rgb;
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// start loading cells from RAM at this hpos value
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// first column read will be ((HLOAD-2) % 32)
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parameter HLOAD = 272;
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output reg [15:0] ram_addr;
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input [15:0] ram_read;
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output reg ram_busy;
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output [10:0] rom_addr;
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input [7:0] rom_data;
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reg [7:0] page_base = 8'h7e; // page table base (8 bits)
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reg [15:0] row_base; // row table base (16 bits)
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reg [4:0] row;
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//wire [4:0] row = vpos[7:3]; // 5-bit row, vpos / 8
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wire [4:0] col = hpos[7:3]; // 5-bit column, hpos / 8
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wire [2:0] yofs = vpos[2:0]; // scanline of cell (0-7)
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wire [2:0] xofs = hpos[2:0]; // which pixel to draw (0-7)
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reg [15:0] cur_cell;
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wire [7:0] cur_char = cur_cell[7:0];
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wire [7:0] cur_attr = cur_cell[15:8];
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// tile ROM address
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assign rom_addr = {cur_char, yofs};
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reg [15:0] row_buffer[0:31];
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// lookup char and attr
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always @(posedge clk) begin
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// reset row to 0 when last row displayed
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if (vpos == 248) begin
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row <= 0;
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end
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// time to read a row?
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if (vpos[2:0] == 7) begin
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// read row_base from page table (2 bytes)
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case (hpos)
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// assert busy 5 cycles before first RAM read
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HLOAD-8: ram_busy <= 1;
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// read page base for row
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HLOAD-3: ram_addr <= {page_base, 3'b000, row};
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HLOAD-1: row_base <= ram_read;
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// deassert BUSY and increment row counter
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HLOAD+34: begin
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ram_busy <= 0;
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row <= row + 1;
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end
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endcase
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// load row of tile data from RAM
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// (last two twice)
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if (hpos >= HLOAD && hpos < HLOAD+34) begin
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ram_addr <= row_base + hpos[4:0];
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row_buffer[hpos[4:0] - 5'd2] <= ram_read;
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end
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end
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// latch character data
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if (hpos < 256) begin
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case (hpos[2:0])
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7: begin
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cur_cell <= row_buffer[col+1];
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end
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endcase
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end else if (hpos == 308) begin
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cur_cell <= row_buffer[0];
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end
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end
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// extract bit from ROM output
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assign rgb = rom_data[~xofs] ? cur_attr[3:0] : cur_attr[7:4];
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endmodule
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