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69 lines
1.2 KiB
Verilog
69 lines
1.2 KiB
Verilog
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`include "hvsync_generator.v"
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`include "font_cp437_8x8.v"
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`include "ram.v"
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`include "tile_renderer.v"
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module test_tilerender_top(clk, reset, out);
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input clk, reset;
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output [1:0] out;
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wire hsync, vsync;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg [15:0] ram_addr;
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wire [15:0] ram_read;
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reg [15:0] ram_write = 0;
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reg ram_writeenable = 0;
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wire [10:0] rom_addr;
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wire [7:0] rom_data;
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wire ram_busy;
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hvsync_generator #(256,60,40,25) hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// RAM
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RAM_sync #(10,16) ram(
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.clk(clk),
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.dout(ram_read),
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.din(ram_write),
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.addr(ram_addr),
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.we(ram_writeenable)
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);
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wire [3:0] rgb_tile;
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tile_renderer tile_gen(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.ram_addr(ram_addr),
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.ram_read(ram_read),
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.ram_busy(ram_busy),
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.rom_addr(rom_addr),
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.rom_data(rom_data),
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.rgb(rgb_tile)
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);
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assign out = (hsync||vsync) ? 0 : (1+rgb_tile[0]+rgb_tile[1]);
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// tile ROM
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font_cp437_8x8 tile_rom(
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.addr(rom_addr),
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.data(rom_data)
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);
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endmodule
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