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43 lines
829 B
Verilog
43 lines
829 B
Verilog
module clock_divider(
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input clk,
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input reset,
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output reg clk_div2,
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output reg clk_div4,
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output reg clk_div8,
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output reg clk_div16,
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output reg [3:0] counter,
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output cntr_div2,
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output cntr_div4,
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output cntr_div8,
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output cntr_div16
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);
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// simple ripple clock divider
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always @(posedge clk)
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clk_div2 <= ~clk_div2;
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always @(posedge clk_div2)
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clk_div4 <= ~clk_div4;
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always @(posedge clk_div4)
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clk_div8 <= ~clk_div8;
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always @(posedge clk_div8)
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clk_div16 <= ~clk_div16;
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// use bits of (4-bit) counter to divide clocks
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always @(posedge clk or posedge reset)
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if (reset)
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counter <= 0;
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else
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counter <= counter + 1;
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assign cntr_div2 = counter[0];
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assign cntr_div4 = counter[1];
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assign cntr_div8 = counter[2];
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assign cntr_div16 = counter[3];
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endmodule
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