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55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
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// ALU operations
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`define OP_ZERO 4'h0
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`define OP_LOAD_A 4'h1
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`define OP_INC 4'h2
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`define OP_DEC 4'h3
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`define OP_ASL 4'h4
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`define OP_LSR 4'h5
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`define OP_ROL 4'h6
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`define OP_ROR 4'h7
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`define OP_OR 4'h8
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`define OP_AND 4'h9
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`define OP_XOR 4'ha
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`define OP_LOAD_B 4'hb
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`define OP_ADD 4'hc
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`define OP_SUB 4'hd
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`define OP_ADC 4'he
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`define OP_SBB 4'hf
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// ALU module
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module ALU(A, B, carry, aluop, Y);
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parameter N = 8; // default width = 8 bits
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input [N-1:0] A; // A input
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input [N-1:0] B; // B input
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input carry; // carry input
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input [3:0] aluop; // alu operation
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output reg [N:0] Y; // Y output + carry
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always @(*)
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case (aluop)
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// unary operations
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`OP_ZERO: Y = 0;
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`OP_LOAD_A: Y = {1'b0, A};
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`OP_INC: Y = A + 1;
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`OP_DEC: Y = A - 1;
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// unary operations that generate and/or use carry
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`OP_ASL: Y = {A, 1'b0};
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`OP_LSR: Y = {A[0], 1'b0, A[N-1:1]};
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`OP_ROL: Y = {A, carry};
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`OP_ROR: Y = {A[0], carry, A[N-1:1]};
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// binary operations
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`OP_OR: Y = {1'b0, A | B};
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`OP_AND: Y = {1'b0, A & B};
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`OP_XOR: Y = {1'b0, A ^ B};
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`OP_LOAD_B: Y = {1'b0, B};
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// binary operations that generate and/or use carry
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`OP_ADD: Y = A + B;
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`OP_SUB: Y = A - B;
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`OP_ADC: Y = A + B + (carry?1:0);
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`OP_SBB: Y = A - B - (carry?1:0);
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endcase
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endmodule
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