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20 lines
375 B
Verilog
20 lines
375 B
Verilog
module LFSR8_11D(
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input clk,
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output reg [7:0] LFSR = 255 // put here the initial value
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);
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wire feedback = LFSR[7];
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always @(posedge clk)
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begin
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LFSR[0] <= feedback;
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LFSR[1] <= LFSR[0];
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LFSR[2] <= LFSR[1] ^ feedback;
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LFSR[3] <= LFSR[2] ^ feedback;
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LFSR[4] <= LFSR[3] ^ feedback;
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LFSR[5] <= LFSR[4];
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LFSR[6] <= LFSR[5];
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LFSR[7] <= LFSR[6];
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end
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endmodule
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