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43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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parameter int SIZES [3:1] = '{10,20,30};
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parameter int SUMS3 = SIZES[3];
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parameter int SUMS2 = SIZES[2];
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parameter int SUMS1 = SIZES[1];
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parameter int LE_SIZES [1:3] = '{10,20,30};
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parameter int LE_SUMS3 = LE_SIZES[3];
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parameter int LE_SUMS2 = LE_SIZES[2];
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parameter int LE_SUMS1 = LE_SIZES[1];
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function int from_array(int index);
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if (index != 0); return SIZES[index];
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endfunction
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function int from_array_le(int index);
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if (index != 0); return LE_SIZES[index];
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endfunction
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initial begin
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if (SUMS1 != 30) $stop;
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if (SUMS2 != 20) $stop;
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if (SUMS3 != 10) $stop;
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if (LE_SUMS1 != 10) $stop;
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if (LE_SUMS2 != 20) $stop;
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if (LE_SUMS3 != 30) $stop;
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if (from_array(1) != 30) $stop;
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if (from_array(2) != 20) $stop;
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if (from_array(3) != 10) $stop;
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if (from_array_le(1) != 10) $stop;
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if (from_array_le(2) != 20) $stop;
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if (from_array_le(3) != 30) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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