Steven Hugg a05ee6680f update parseHexWords regex to make Verilog binary separate case		2019-07-18 22:37:05 -04:00
..
6502	disasm z80 fixes; no recording btn for verilog	2018-08-28 06:17:32 -07:00
verilog	verilog: scope updates, show js code, simple cpu	2017-11-28 20:38:48 -05:00
z80	generate z80 cpu on demand like we used to, fix test b/c global.z80 is global	2019-05-17 00:09:43 -04:00
test1.c	more work on vector game; williams examples, tools	2017-03-30 17:14:45 -04:00
testasm.js	converted Assembler to class, added nanoasm submodule (not mapped yet)	2019-05-25 21:51:01 -04:00
testdecoder.js	converted src/platform to typescript; stack debug view	2018-08-16 22:30:51 -04:00
testgithub.js	github: each repo in a separate localstorage key	2019-05-26 10:55:02 -04:00
testpixelconvert.js	update parseHexWords regex to make Verilog binary separate case	2019-07-18 22:37:05 -04:00
testplatforms.js	astrocade debug fixes; z80 was borking 'im' during loadState()	2019-05-28 19:22:11 -04:00
teststore.js	convert loadFiles() to Promise	2019-05-23 08:32:53 -04:00
testutil.js	verilog: support $readmemb/h("file", array)	2019-05-01 23:43:06 -04:00
testverilog.js	>32-bit warning for verilog	2018-12-30 13:29:38 -06:00
testworker.js	astrocade: split bios into .c files; check rom_size on sdcc targets (not yet)	2019-06-02 22:49:51 -04:00
workertestutils.js	write README when creating github repository, check platform, migrate files	2019-05-08 12:18:54 -04:00