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73 lines
1.5 KiB
Verilog
73 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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// surefire lint_off _NETNM
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// surefire lint_off STMINI
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input clk;
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integer _mode; initial _mode = 0;
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wire [2:0] b3; reg [2:0] g3;
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wire [5:0] b6; reg [5:0] g6;
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t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
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t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
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always @ (posedge clk) begin
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if (_mode==0) begin
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_mode <= 1;
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g3 <= 3'b101;
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g6 <= 6'b110101;
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end
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else if (_mode==1) begin
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if (b3 !== 3'b110) $stop;
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if (b6 !== 6'b100110) $stop;
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_mode <= 2;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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// Module gray2bin
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// convert an arbitrary width gray coded number to binary. The conversion
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// of a 4 bit gray (represented as "g") to binary ("b") would go as follows:
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// b[3] = ^g[3] = g[3]
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// b[2] = ^g[3:2]
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// b[1] = ^g[3:1]
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// b[0] = ^g[3:[SZ-1:0] cur0]
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module t_func_grey2bin (/*AUTOARG*/
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// Outputs
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b,
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// Inputs
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g
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);
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// surefire lint_off STMFOR
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parameter SZ = 5;
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output [SZ-1:0] b;
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input [SZ-1:0] g;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg [SZ-1:0] b;
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// End of automatics
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integer i;
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always @(/*AUTOSENSE*/g)
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for (i=0; i<SZ; i=i+1)
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b[i] = ^(g >> i); // surefire lint_off_line LATASS
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endmodule
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