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65 lines
1.4 KiB
Verilog
65 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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// verilator lint_off WIDTH
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`define INT_RANGE 31:0
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`define INT_RANGE_MAX 31
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`define VECTOR_RANGE 63:0
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reg [`INT_RANGE] stashb, stasha, stashn, stashm;
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function [`VECTOR_RANGE] copy_range;
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input [`VECTOR_RANGE] y;
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input [`INT_RANGE] b;
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input [`INT_RANGE] a;
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input [`VECTOR_RANGE] x;
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input [`INT_RANGE] n;
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input [`INT_RANGE] m;
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begin
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copy_range = y;
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stashb = b;
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stasha = a;
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stashn = n;
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stashm = m;
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end
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endfunction
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parameter DATA_SIZE = 16;
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parameter NUM_OF_REGS = 32;
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reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf;
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reg [DATA_SIZE-1:0] memread_rf_reg;
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always @(memread_rf) begin : memread_convert
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memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf,
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DATA_SIZE-'d1, DATA_SIZE-'d1);
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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memread_rf = 512'haa;
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end
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if (cyc==3) begin
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if (stashb != 'd15) $stop;
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if (stasha != 'd15) $stop;
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if (stashn != 'd15) $stop;
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if (stashm != 'd15) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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