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73 lines
1.4 KiB
Verilog
73 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Test generate index usage.
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//
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// The code illustrates a problem in Verilator's handling of constant
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// expressions inside generate indexes.
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//
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// This is a regression test against issue 517.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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`define START 8
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`define SIZE 4
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`define END (`START + `SIZE)
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [`END-1:0] y;
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wire [`END-1:0] x;
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foo foo_i (.y (y),
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.x (x),
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.clk (clk));
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule // t
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module foo(output wire [`END-1:0] y,
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input wire [`END-1:0] x,
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input wire clk);
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function peek_bar;
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peek_bar = bar_inst[`START].i_bar.r; // this is ok
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peek_bar = bar_inst[`START + 1].i_bar.r; // this fails, should not.
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endfunction
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genvar g;
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generate
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for (g = `START; g < `END; g = g + 1) begin: bar_inst
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bar i_bar(.x (x[g]),
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.y (y[g]),
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.clk (clk));
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end
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endgenerate
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endmodule : foo
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module bar(output wire y,
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input wire x,
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input wire clk);
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reg r = 0;
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assign y = r;
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always @(posedge clk) begin
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r = x ? ~x : y;
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end
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endmodule : bar
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