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36 lines
551 B
Verilog
36 lines
551 B
Verilog
// DESCRIPTION: Verilator: SystemVerilog interface test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Thierry Tambe.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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sub sub [1] ();
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ahb_slave_intf AHB_S[1]();
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AHB_MEM uMEM(.S(AHB_S[0]));
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// AHB_MEM uMEM(.S(AHB_S[0].source));
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endmodule
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module sub;
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endmodule
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module AHB_MEM
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(
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ahb_slave_intf.source S
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);
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endmodule
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interface ahb_slave_intf
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();
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logic [31:0] HADDR;
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modport source (input HADDR);
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endinterface
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