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73 lines
1.5 KiB
Verilog
73 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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wire [31:0] out1;
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wire [31:0] out2;
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sub sub (.in1(crc[15:0]), .in2(crc[31:16]), .out1(out1), .out2);
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x sum=%x out=%x %x\n",$time, cyc, crc, sum, out1, out2);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1};
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if (cyc==1) begin
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// Setup
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crc <= 64'h00000000_00000097;
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sum <= 64'h0;
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end
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else if (cyc==90) begin
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if (sum !== 64'he396068aba3898a2) $stop;
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end
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else if (cyc==91) begin
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end
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else if (cyc==92) begin
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end
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else if (cyc==93) begin
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end
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else if (cyc==94) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (/*AUTOARG*/
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// Outputs
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out1, out2,
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// Inputs
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in1, in2
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);
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input [15:0] in1;
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input [15:0] in2;
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output reg signed [31:0] out1;
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output reg unsigned [31:0] out2;
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always @* begin
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// verilator lint_off WIDTH
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out1 = $signed(in1) * $signed(in2);
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out2 = $unsigned(in1) * $unsigned(in2);
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// verilator lint_on WIDTH
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end
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endmodule
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