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33 lines
972 B
Verilog
33 lines
972 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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`timescale 1ns/1ps
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module t;
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time t;
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// realtime value scaled to timeunit, rounded to timeprecision
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initial begin
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// verilator lint_off REALCVT
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t = 1s; `checkd(t, 64'd1000000000);
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t = 2ms; `checkd(t, 2000000);
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t = 1ms; `checkd(t, 1000000);
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t = 1us; `checkd(t, 1000);
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t = 1ns; `checkd(t, 1);
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t = 1ps; `checkd(t, 0); // Below precision
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t = 1fs; `checkd(t, 0);
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t = 2.3ps; `checkd(t, 0);
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t = 2.4us; `checkd(t, 2400);
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// verilator lint_on REALCVT
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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