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112 lines
3.2 KiB
Verilog
112 lines
3.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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fastclk, clk
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);
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`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge
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`define posstyle posedge
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`define negstyle negedge
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`else
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`define posstyle
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`define negstyle
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`endif
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input fastclk;
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input clk;
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reg [7:0] data;
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reg [7:0] data_a;
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reg [7:0] data_a_a;
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reg [7:0] data_a_b;
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reg [7:0] data_b;
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reg [7:0] data_b_a;
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reg [7:0] data_b_b;
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reg [8*6-1:0] check [100:0];
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wire [8*6-1:0] compare = {data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b};
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initial begin
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check[7'd19] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
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check[7'd20] = {8'h0d, 8'h0e, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
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check[7'd21] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
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check[7'd22] = {8'h15, 8'h16, 8'h0e, 8'h0d, 8'h0e, 8'h0e};
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check[7'd23] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
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check[7'd24] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
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check[7'd25] = {8'h15, 8'h16, 8'h0e, 8'h15, 8'h16, 8'h0e};
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check[7'd26] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
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check[7'd27] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h0e};
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check[7'd28] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
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check[7'd29] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
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check[7'd30] = {8'h15, 8'h16, 8'h16, 8'h15, 8'h16, 8'h16};
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check[7'd31] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
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check[7'd32] = {8'h1f, 8'h20, 8'h16, 8'h15, 8'h16, 8'h16};
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check[7'd33] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
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check[7'd34] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
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check[7'd35] = {8'h1f, 8'h20, 8'h16, 8'h1f, 8'h20, 8'h16};
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check[7'd36] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
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check[7'd37] = {8'h1f, 8'h20, 8'h20, 8'h1f, 8'h20, 8'h16};
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end
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// verilator lint_off COMBDLY
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// verilator lint_off LATCH
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always @ (`posstyle clk /*AS*/ or data) begin
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if (clk) begin
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data_a <= data + 8'd1;
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end
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end
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always @ (`posstyle clk /*AS*/ or data_a) begin
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if (clk) begin
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data_a_a <= data_a + 8'd1;
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end
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end
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always @ (`posstyle clk /*AS*/ or data_b) begin
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if (clk) begin
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data_b_a <= data_b + 8'd1;
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end
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end
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always @ (`negstyle clk /*AS*/ or data or data_a) begin
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if (~clk) begin
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data_b <= data + 8'd1;
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data_a_b <= data_a + 8'd1;
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data_b_b <= data_b + 8'd1;
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end
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end
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integer cyc; initial cyc=0;
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always @ (posedge fastclk) begin
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cyc <= cyc+1;
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`ifdef TEST_VERBOSE
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$write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b);
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`endif
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if (cyc>=19 && cyc<36) begin
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if (compare !== check[cyc]) begin
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$write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]);
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$stop;
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end
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end
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if (cyc == 10) begin
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data <= 8'd12;
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end
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if (cyc == 20) begin
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data <= 8'd20;
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end
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if (cyc == 30) begin
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data <= 8'd30;
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end
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if (cyc == 40) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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