mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-11-22 14:33:51 +00:00
12 lines
266 B
Verilog
12 lines
266 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2020 by Edgar E. Iglesias.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t (
|
|
clk
|
|
);
|
|
input clk;
|
|
endmodule
|