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82 lines
1.9 KiB
Verilog
82 lines
1.9 KiB
Verilog
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`ifndef RAM_H
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`define RAM_H
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/*
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RAM_sync - Synchronous RAM module.
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RAM_async - Asynchronous RAM module.
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RAM_async_tristate - Async RAM module with bidirectional data bus.
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Module parameters:
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A - number of address bits (default = 10)
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D - number of data bits (default = 8)
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*/
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module RAM_sync(clk, addr, din, dout, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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input clk; // clock
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input [A-1:0] addr; // address
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input [D-1:0] din; // data input
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input we; // write enable
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output reg [D-1:0] dout; // data output
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reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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dout <= mem[addr]; // read memory to dout (sync)
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end
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endmodule
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module RAM_async(clk, addr, din, dout, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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input clk; // clock
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input [A-1:0] addr; // address
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input [D-1:0] din; // data input
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output [D-1:0] dout; // data output
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input we; // write enable
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reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= din; // write memory from din
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end
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assign dout = mem[addr]; // read memory to dout (async)
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endmodule
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module RAM_async_tristate(clk, addr, data, we);
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parameter A = 10; // # of address bits
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parameter D = 8; // # of data bits
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input clk; // clock
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input [A-1:0] addr; // address
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inout [D-1:0] data; // data in/out
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input we; // write enable
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reg [D-1:0] mem [0:(1<<A)-1]; // (1<<A)xD bit memory
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always @(posedge clk) begin
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if (we) // if write enabled
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mem[addr] <= data; // write memory from data
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end
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assign data = !we ? mem[addr] : {D{1'bz}}; // read memory to data (async)
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endmodule
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`endif
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