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70 lines
2.2 KiB
Verilog
70 lines
2.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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wire d1 = 1'b1;
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wire d2 = 1'b1;
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wire d3 = 1'b1;
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wire o1,o2,o3;
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add1 add1 (d1,o1);
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add2 add2 (d2,o2);
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`define ls left_side
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`define rs right_side
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`define noarg na//note extra space
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`define thru(x) x
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`define thruthru `ls `rs // Doesn't expand
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`define msg(x,y) `"x: `\`"y`\`"`"
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`define left(m,left) m // The 'left' as the variable name shouldn't match the "left" in the `" string
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initial begin
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//$display(`msg( \`, \`)); // Illegal
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$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
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$display(`msg(left side,right side));
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$display(`msg( left side , right side ));
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$display(`msg( `ls , `rs ));
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$display(`msg( `noarg , `rs ));
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$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
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$display(`msg(`noarg,`noarg`noarg));
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$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
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$display(`left(`msg( left side , right side ), left_replaced));
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//$display(`msg( `"tickquoted_left`", `"tickquoted_right`" )); // Syntax error
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`ifndef VCS // Sim bug - wrong number of arguments, but we're right
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$display(`msg(`thru(),)); // Empty
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`endif
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$display(`msg(`thru(left side),`thru(right side)));
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$display(`msg( `thru( left side ) , `thru( right side ) ));
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`ifndef NC
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$display(`"standalone`");
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`endif
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`ifdef VERILATOR
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// Illegal on some simulators, as the "..." crosses two lines
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`define twoline first \
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second
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$display(`msg(twoline, `twoline));
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`endif
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$display("Line %0d File \"%s\"",`__LINE__,`__FILE__);
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//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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`define ADD_UP(a,c) \
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wire tmp_``a = a; \
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wire tmp_``c = tmp_``a + 1; \
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assign c = tmp_``c ;
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module add1 ( input wire d1, output wire o1);
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`ADD_UP(d1,o1) // expansion is OK
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endmodule
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module add2 ( input wire d2, output wire o2);
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`ADD_UP( d2 , o2 ) // expansion is bad
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endmodule
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// `ADD_UP( \d3 , \o3 ) // This really is illegal
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