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127 lines
2.5 KiB
Verilog
127 lines
2.5 KiB
Verilog
`include "hvsync_generator.v"
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`include "font_cp437_8x8.v"
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`include "ram.v"
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`include "tile_renderer.v"
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`include "sprite_scanline_renderer.v"
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`include "lfsr.v"
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`include "sound_generator.v"
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`include "cpu8.v"
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`include "cpu16.v"
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module maze_game_top(clk, reset, hsync, vsync, rgb);
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input clk, reset;
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output hsync, vsync;
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output [3:0] rgb;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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// video RAM bus
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wire [7:0] vram_read;
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reg [7:0] vram_write = 0;
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reg vram_writeenable = 0;
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// multiplex sprite and tile RAM
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wire sprite_ram_select = (vpos == 256);
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reg [15:0] tile_ram_addr;
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reg [6:0] sprite_ram_addr;
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// tile and sprite ROM
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wire [10:0] tile_rom_addr;
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wire [7:0] tile_rom_data;
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wire [15:0] sprite_rom_addr;
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wire [15:0] sprite_rom_data;
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// gfx outputs
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wire [3:0] tile_rgb;
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wire [3:0] sprite_rgb;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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// video RAM (16k)
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RAM #(14,8) vram(
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.clk(clk),
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.dout(vram_read),
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.din(vram_write),
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.addr(sprite_ram_select
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? {7'b0111111, sprite_ram_addr}
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: tile_ram_addr[13:0]),
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.we(vram_writeenable)
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);
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tile_renderer tile_gen(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.display_on(display_on),
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.ram_addr(tile_ram_addr),
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.ram_read(vram_read),
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.rom_addr(tile_rom_addr),
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.rom_data(tile_rom_data),
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.rgb(tile_rgb)
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);
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sprite_scanline_renderer ssr(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.ram_addr(sprite_ram_addr),
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.ram_data(vram_read),
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.rom_addr(sprite_rom_addr),
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.rom_data(sprite_rom_data),
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.rgb(sprite_rgb)
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);
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font_cp437_8x8 tile_rom(
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.addr(tile_rom_addr),
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.data(tile_rom_data)
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);
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example_bitmap_rom bitmap_rom(
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.addr(sprite_rom_addr),
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.data(sprite_rom_data)
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);
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assign rgb = display_on
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? (sprite_rgb>0 ? sprite_rgb : tile_rgb)
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: 0;
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// CPU RAM (32k x 16 bits)
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RAM #(15,16) mram(
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.clk(clk),
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.dout(cpuram_read),
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.din(cpuram_write),
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.addr(cpuram_addr[14:0]),
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.we(cpuram_writeenable)
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);
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reg [15:0] cpuram_read;
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reg [15:0] cpuram_write;
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reg [15:0] cpuram_addr;
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reg cpuram_writeenable;
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wire busy;
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CPU16 cpu(
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.clk(clk),
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.reset(reset),
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.hold(0),
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.busy(busy),
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.address(cpuram_addr),
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.data_in(cpuram_read),
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.data_out(cpuram_write),
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.write(cpuram_writeenable));
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endmodule
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