98 lines
2.6 KiB
Verilog
98 lines
2.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish;
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// on success, or $stop.
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//
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// The code as shown applies a random vector to the Test
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// module, then calculates a CRC on the Test module's outputs.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] out; // From test of Test.v
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// End of automatics
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Test test(/*AUTOINST*/
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// Outputs
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.out (out[31:0]),
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// Inputs
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.clk (clk),
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.in (in[31:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4afe43fb79d7b71e
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in
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);
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// Replace this module with the device under test.
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//
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// Change the code in the t module to apply values to the inputs and
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// merge the output values into the result vector.
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input clk;
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input [31:0] in;
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output reg [31:0] out;
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always @(posedge clk) begin
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out <= in;
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end
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endmodule
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