67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Driss Hafdi.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, rst
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);
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input clk;
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input rst;
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logic [2:0] ctrl_inc_single;
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logic [2:0] ctrl_inc_double;
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logic [2:0] cnt_single;
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always_ff @(posedge clk) begin
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if (rst) begin
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cnt_single <= '0;
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end
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else if (ctrl_inc_single != '0 && cnt_single != '1) begin
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cnt_single <= cnt_single + 1'd1;
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end
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end
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logic [2:0] cnt_double;
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always_ff @(posedge clk) begin
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if (rst) begin
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cnt_double <= '0;
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end
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else if (ctrl_inc_double != '0 && cnt_double != '1) begin
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cnt_double <= cnt_double + 1'd1;
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end
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end
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always_comb ctrl_inc_single = '0;
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always_comb ctrl_inc_double = '0;
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testMod test_i (.data_i(cnt_single));
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testMod test_j (.data_i(cnt_double));
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module testMod
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(input wire [2:0] data_i);
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typedef logic [63:0] time_t;
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time_t [2:0] last_transition;
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genvar b;
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generate
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for (b = 0; b <= 2; b++) begin : gen_trans
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always_ff @(posedge data_i[b] or negedge data_i[b]) begin
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last_transition[b] <= $time;
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end
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end
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endgenerate
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endmodule
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