40 lines
763 B
Verilog
40 lines
763 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOINST*/);
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Test #(
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.BIT_WIDTH (72),
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.BYTE_WIDTH (9)
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)
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u_test_inst();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Test ();
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parameter BIT_WIDTH = "";
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parameter BYTE_WIDTH = "";
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localparam BYTES = BIT_WIDTH / BYTE_WIDTH;
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wire [BYTES - 1:0] i;
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wire [BYTES - 1:0] o;
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genvar g;
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generate
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for (g = 0; g < BYTES; g = g + 1) begin: gen
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assign o[g] = (i[g] !== 1'b0);
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end
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endgenerate
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endmodule
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