85 lines
1.5 KiB
Verilog
85 lines
1.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire b;
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reg reset;
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integer cyc=0;
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Testit testit (/*AUTOINST*/
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// Outputs
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.b (b),
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// Inputs
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.clk (clk),
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.reset (reset));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc==0) begin
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reset <= 1'b0;
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end
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else if (cyc<10) begin
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reset <= 1'b1;
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end
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else if (cyc<90) begin
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reset <= 1'b0;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Testit (clk, reset, b);
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input clk;
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input reset;
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output b;
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wire [0:0] c;
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wire my_sig;
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wire [0:0] d;
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genvar i;
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generate
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for(i = 0; i >= 0; i = i-1) begin: fnxtclk1
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fnxtclk fnxtclk1
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(.u(c[i]),
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.reset(reset),
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.clk(clk),
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.w(d[i]) );
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end
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endgenerate
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assign b = d[0];
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assign c[0] = my_sig;
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assign my_sig = 1'b1;
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endmodule
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module fnxtclk (u, reset, clk, w );
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input u;
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input reset;
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input clk;
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output reg w;
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always @ (posedge clk or posedge reset) begin
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if (reset == 1'b1) begin
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w <= 1'b0;
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end
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else begin
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w <= u;
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end
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end
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endmodule
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