33 lines
657 B
Verilog
33 lines
657 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Johan Bjork.
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// SPDX-License-Identifier: CC0-1.0
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parameter N = 5;
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interface intf;
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logic [N-1:0] data;
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endinterface
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module t (
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input logic clk
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);
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intf localinterface [N-1:0]();
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generate
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genvar i,j;
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for(i = 0; i < N; i++) begin
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logic [N-1:0] dummy;
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for(j = 0; j < N; j++) begin
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assign dummy[j] = localinterface[j].data[i];
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end
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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