133 lines
3.0 KiB
Verilog
133 lines
3.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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localparam WIDTH = 31;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [WIDTH-1:0] b; // From test of Test.v
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wire [WIDTH-1:0] c; // From test of Test.v
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// End of automatics
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reg rst_l;
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Test #(.WIDTH(WIDTH))
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test (/*AUTOINST*/
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// Outputs
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.b (b[WIDTH-1:0]),
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.c (c[WIDTH-1:0]),
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// Inputs
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.clk (clk),
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.rst_l (rst_l),
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.in (in[WIDTH-1:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {1'h0, c, 1'b0, b};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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rst_l <= ~1'b1;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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rst_l <= ~1'b1;
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// Hold reset while summing
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end
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else if (cyc<20) begin
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rst_l <= ~1'b0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'hbcfcebdb75ec9d32
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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b, c,
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// Inputs
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clk, rst_l, in
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);
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parameter WIDTH = 5;
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input clk;
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input rst_l;
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input [WIDTH-1:0] in;
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output wire [WIDTH-1:0] b;
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output wire [WIDTH-1:0] c;
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dff # ( .WIDTH (WIDTH),
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.RESET ('0), // Although this is a single bit, the parameter must be the specified type
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.RESET_WIDTH (1) )
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sub1
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( .clk(clk), .rst_l(rst_l), .q(b), .d(in) );
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dff # ( .WIDTH (WIDTH),
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.RESET ({ 1'b1, {(WIDTH-1){1'b0}} }),
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.RESET_WIDTH (WIDTH))
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sub2
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( .clk(clk), .rst_l(rst_l), .q(c), .d(in) );
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endmodule
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module dff (/*AUTOARG*/
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// Outputs
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q,
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// Inputs
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clk, rst_l, d
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);
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parameter WIDTH = 1;
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parameter RESET = {WIDTH{1'b0}};
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parameter RESET_WIDTH = WIDTH;
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input clk;
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input rst_l;
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input [WIDTH-1:0] d;
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output reg [WIDTH-1:0] q;
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always_ff @(posedge clk or negedge rst_l) begin
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if ($bits(RESET) != RESET_WIDTH) $stop;
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// verilator lint_off WIDTH
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if (~rst_l) q <= RESET;
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// verilator lint_on WIDTH
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else q <= d;
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end
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endmodule
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