43 lines
784 B
Verilog
43 lines
784 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Alex Solomatnikov.
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// SPDX-License-Identifier: CC0-1.0
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//bug595
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [6-1:0] foo; initial foo = 20;
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dut #(.W(6)) udut(.clk(clk),
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.foo(foo-16));
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endmodule
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module dut
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#(parameter W = 1)
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(input logic clk,
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input logic [W-1:0] foo);
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genvar i;
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generate
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for (i = 0; i < W; i++) begin
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suba ua(.clk(clk), .foo(foo[i]));
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end
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endgenerate
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endmodule
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module suba
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(input logic clk,
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input logic foo);
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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