60 lines
948 B
Verilog
60 lines
948 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// A test of the import parameter used with modport
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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interface test_if;
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// Interface variable
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logic data;
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// Modport
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modport mp(
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import myfunc,
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output data
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);
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function automatic logic myfunc (input logic val);
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begin
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myfunc = (val == 1'b0);
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end
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endfunction
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endinterface // test_if
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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test_if i ();
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testmod testmod_i (.clk (clk),
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.i (i.mp));
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endmodule
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module testmod
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(
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input clk,
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test_if.mp i
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);
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always @(posedge clk) begin
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i.data = 1'b0;
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if (i.myfunc (1'b0)) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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