75 lines
1.8 KiB
Verilog
75 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer _mode;
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reg _guard1;
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reg [127:0] r_wide0;
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reg _guard2;
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wire [63:0] r_wide1;
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reg _guard3;
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reg _guard4;
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reg _guard5;
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reg _guard6;
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assign r_wide1 = r_wide0[127:64];
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// surefire lint_off STMINI
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initial _mode = 0;
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always @ (posedge clk) begin
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if (_mode==0) begin
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$write("[%0t] t_equal: Running\n", $time);
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_guard1 <= 0;
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_guard2 <= 0;
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_guard3 <= 0;
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_guard4 <= 0;
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_guard5 <= 0;
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_guard6 <= 0;
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_mode<=1;
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r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
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end
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else if (_mode==1) begin
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_mode<=2;
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//
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if (5'd10 != 5'b1010) $stop;
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if (5'd10 != 5'd10) $stop;
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if (5'd10 != 5'd1_0) $stop;
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if (5'd10 != 5'ha) $stop;
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if (5'd10 != 5'o12) $stop;
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if (5'd10 != 5'o1_2) $stop;
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if (5'd10 != 5'B 1010) $stop;
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if (5'd10 != 5'B 10_10) $stop;
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if (5'd10 != 5'D10) $stop;
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if (5'd10 != 5'H a) $stop;
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if (5'd10 != 5 'O 12) $stop;
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if (24'h29cbb8 != 24'o12345670) $stop;
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if (24'h29__cbb8 != 24'o123456__70) $stop;
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if (6'b111xxx !== 6'o7x) $stop;
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if (6'b111??? !== 6'o7?) $stop;
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if (6'b111zzz !== 6'o7z) $stop;
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//
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if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
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if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
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if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
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$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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