38 lines
969 B
Verilog
38 lines
969 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/);
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// signed source
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logic signed [8-1:0] src;
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// destination structure
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struct packed {
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logic signed [16-1:0] s;
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logic unsigned [16-1:0] u;
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} dst;
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initial begin
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// bug882
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// verilator lint_off WIDTH
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src = 8'sh05;
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dst = '{s: src, u: src};
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`checkh (dst.s, 16'h0005);
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`checkh (dst.u, 16'h0005);
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src = 8'shf5;
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dst = '{s: src, u: src};
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`checkh (dst.s, 16'hfff5);
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`checkh (dst.u, 16'hfff5);
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// verilator lint_on WIDTH
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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