60 lines
1.3 KiB
Verilog
60 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2014 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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// See also t_lint_width
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parameter A_ONE = '1;
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// verilator lint_off WIDTH
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parameter [3:0] A_W4 = A_ONE;
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// verilator lint_on WIDTH
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initial begin
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if ($bits(A_ONE) != 1 || A_ONE !== 1'b1) $stop;
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if ($bits(A_W4) != 4) $stop;
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if (A_W4 != 4'b0001) $stop;
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end
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b #(.B_WIDTH(48)) b ();
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reg [4:0] c;
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integer c_i;
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initial begin
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c_i = 3;
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c = 1'b1 << c_i; // No width warning when not embedded in expression, as is common syntax
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if (c != 5'b1000) $stop;
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end
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localparam D_TT = 32'd23;
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localparam D_SIX = 6;
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// verilator lint_off WIDTH
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localparam [5:0] D_SUB = D_TT - D_SIX;
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// verilator lint_on WIDTH
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initial begin
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if (D_SUB != 17) $stop;
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end
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module b;
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parameter B_WIDTH = 1;
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localparam B_VALUE0 = {B_WIDTH{1'b0}};
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localparam B_VALUE1 = {B_WIDTH{1'b1}};
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reg [47:0] b_val;
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initial begin
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b_val = B_VALUE0;
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if (b_val != 48'b0) $stop;
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b_val = B_VALUE1;
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if (b_val != ~48'b0) $stop;
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end
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endmodule
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