85 lines
2.6 KiB
Verilog
85 lines
2.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 Claire Wolf.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] y1; // From d1 of demo_001.v
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wire [7:0] y2; // From d1 of demo_001.v
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wire [7:0] y3; // From d1 of demo_001.v
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wire [7:0] y4; // From d1 of demo_001.v
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wire [31:0] z0; // From d2 of demo_002.v
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wire [31:0] z1; // From d2 of demo_002.v
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wire [31:0] z2; // From d2 of demo_002.v
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wire [31:0] z3; // From d2 of demo_002.v
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// End of automatics
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demo_001 d1(/*AUTOINST*/
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// Outputs
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.y1 (y1[7:0]),
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.y2 (y2[7:0]),
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.y3 (y3[7:0]),
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.y4 (y4[7:0]));
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demo_002 d2(/*AUTOINST*/
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// Outputs
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.z0 (z0[31:0]),
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.z1 (z1[31:0]),
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.z2 (z2[31:0]),
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.z3 (z3[31:0]));
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (y1 !== 8'h7b) $stop;
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if (y2 !== 8'h7c) $stop;
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if (y3 !== 8'h7b) $stop;
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if (y4 !== 8'h7c) $stop;
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if (z0 !== 32'h00000000) $stop;
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if (z1 !== 32'hffffffff) $stop;
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if (z2 !== 32'hffffffff) $stop;
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if (z3 !== 32'hffffffff) $stop;
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module demo_001(y1, y2, y3, y4);
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output [7:0] y1, y2, y3, y4;
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// verilator lint_off REALCVT
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localparam [7:0] p1 = 123.45;
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localparam real p2 = 123.45;
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localparam real p3 = 123;
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localparam p4 = 123.45;
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// verilator lint_off WIDTH
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assign y1 = p1 + 0.2;
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assign y2 = p2 + 0.2;
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assign y3 = p3 + 0.2;
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assign y4 = p4 + 0.2;
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// verilator lint_on WIDTH
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endmodule
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module demo_002(z0, z1, z2, z3);
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output [31:0] z0, z1, z2, z3;
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// verilator lint_off WIDTH
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assign z0 = 1'bx >= (-1 * -1.17);
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// verilator lint_on WIDTH
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assign z1 = 1 ? 1 ? -1 : 'd0 : 0.0;
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assign z2 = 1 ? -1 : 1 ? 'd0 : 0.0;
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assign z3 = 1 ? -1 : 'd0;
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endmodule
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