74 lines
1.8 KiB
Verilog
74 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2017 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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reg [5:0] addr;
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parameter BANKS = 6;
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parameter ROWS = 8;
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wire [2:0] bank;
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wire [2:0] row;
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integer a;
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integer used[BANKS][ROWS];
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// Test loop
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initial begin
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for (a = 0; a < BANKS*ROWS; ++a) begin
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addr[5:0] = a[5:0];
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hash (addr, bank, row);
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used [bank][row] ++;
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if (used [bank][row] > 1) begin
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$write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row);
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end
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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task hash (input [5:0] addr,
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output [2:0] bank,
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output [2:0] row);
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reg [1:0] third;
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reg [1:0] fourth;
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third = {addr[5], addr[4]};
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fourth = {addr[3] ^ addr[1],
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addr[2] ^ addr[0]};
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case (third)
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2'h0:
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case (fourth)
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2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end
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2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end
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2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end
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2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end
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endcase
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2'h1:
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case (fourth)
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2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end
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2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end
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2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end
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2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end
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endcase
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2'h2:
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case (fourth)
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2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end
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2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end
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2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end
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2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end
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endcase
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2'h3: $stop;
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endcase
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endtask
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endmodule
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