112 lines
2.7 KiB
Verilog
112 lines
2.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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wire [65:0] outData; // From fifo of fifo.v
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wire [15:0] inData = crc[15:0];
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wire [1:0] inWordPtr = crc[17:16];
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wire wrEn = crc[20];
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wire [1:0] wrPtr = crc[33:32];
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wire [1:0] rdPtr = crc[34:33];
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fifo fifo (
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// Outputs
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.outData (outData[65:0]),
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// Inputs
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.clk (clk),
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.inWordPtr (inWordPtr[1:0]),
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.inData (inData[15:0]),
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.rdPtr (rdPtr),
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.wrPtr (wrPtr),
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.wrEn (wrEn));
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc==90) begin
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if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
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end
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else if (cyc==91) begin
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if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
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end
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else if (cyc==92) begin
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if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
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end
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else if (cyc==93) begin
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if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
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end
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else if (cyc==94) begin
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if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module fifo (/*AUTOARG*/
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// Outputs
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outData,
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// Inputs
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clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
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);
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parameter fifoDepthLog2 = 1;
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parameter fifoDepth = 1<<fifoDepthLog2;
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`define PTRBITS (fifoDepthLog2+1)
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`define PTRBITSM1 fifoDepthLog2
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`define PTRBITSM2 (fifoDepthLog2-1)
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input clk;
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input [1:0] inWordPtr;
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input [15:0] inData;
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input [`PTRBITSM1:0] wrPtr;
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input [`PTRBITSM1:0] rdPtr;
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output [65:0] outData;
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input wrEn;
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reg [65:0] outData;
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// verilator lint_off VARHIDDEN
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// verilator lint_off LITENDIAN
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reg [65:0] fifo[0:fifoDepth-1];
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// verilator lint_on LITENDIAN
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// verilator lint_on VARHIDDEN
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//reg [65:0] temp;
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always @(posedge clk) begin
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//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
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if (wrEn) begin
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fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
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// Equivelent to:
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//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
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//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
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//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
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end
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outData <= fifo[rdPtr[`PTRBITSM2:0]];
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end
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endmodule
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