125 lines
2.7 KiB
Verilog
125 lines
2.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [2:0] q; // From test of Test.v
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// End of automatics
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Test test (
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// Outputs
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.q (q[2:0]),
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// Inputs
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.clk (clk),
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.reset_l (crc[0]),
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.enable (crc[2]),
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.q_var0 (crc[19:10]),
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.q_var2 (crc[29:20]),
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.q_var4 (crc[39:30]),
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.q_var6 (crc[49:40])
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/*AUTOINST*/);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {61'h0,q};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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`define EXPECTED_SUM 64'h58b162c58d6e35ba
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test
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(
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input clk,
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input reset_l,
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input enable,
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input [ 9:0] q_var0,
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input [ 9:0] q_var2,
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input [ 9:0] q_var4,
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input [ 9:0] q_var6,
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output reg [2:0] q
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);
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reg [7:0] p1_r [6:0];
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always @(posedge clk) begin
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if (!reset_l) begin
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p1_r[0] <= 'b0;
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p1_r[1] <= 'b0;
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p1_r[2] <= 'b0;
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p1_r[3] <= 'b0;
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p1_r[4] <= 'b0;
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p1_r[5] <= 'b0;
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p1_r[6] <= 'b0;
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end
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else if (enable) begin : pass1
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match(q_var0, q_var2, q_var4, q_var6);
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end
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end
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// verilator lint_off WIDTH
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always @(posedge clk) begin : l
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reg [10:0] bd;
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reg [3:0] idx;
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q = 0;
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bd = 0;
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for (idx=0; idx<7; idx=idx+1) begin
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q = idx+1;
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bd = bd + p1_r[idx];
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end
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end
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task match;
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input [9:0] p0, p1, p2, p3;
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reg [9:0] p[3:0];
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begin
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p[0] = p0;
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p[1] = p1;
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p[2] = p2;
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p[3] = p3;
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p1_r[0] <= p[0];
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p1_r[1] <= p[1];
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end
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endtask
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endmodule
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