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36 lines
880 B
Verilog
36 lines
880 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This files is used to generated the following error:
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// %Error: Internal Error: t/t_unroll_forfor.v:27: ../V3Simulate.h:177: No value found for node.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Jan Egil Ruud.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [71:0] in;
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reg [71:0] in_tmp;
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localparam [71:0] TEST_PARAM = {72{1'b0}};
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// Test loop
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always @*
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begin: testmap
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byte i, j;
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// bug1044
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for ( i = 0; i < 9; i = i + 1 )
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// verilator lint_off WIDTH
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for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin
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in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j];
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end
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// verilator lint_on WIDTH
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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