mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-12-23 03:29:39 +00:00
98 lines
2.6 KiB
Verilog
98 lines
2.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// Use this file as a template for submitting bugs, etc.
|
|
// This module takes a single clock input, and should either
|
|
// $write("*-* All Finished *-*\n");
|
|
// $finish;
|
|
// on success, or $stop.
|
|
//
|
|
// The code as shown applies a random vector to the Test
|
|
// module, then calculates a CRC on the Test module's outputs.
|
|
//
|
|
// **If you do not wish for your code to be released to the public
|
|
// please note it here, otherwise:**
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t(/*AUTOARG*/
|
|
// Inputs
|
|
clk
|
|
);
|
|
input clk;
|
|
|
|
integer cyc=0;
|
|
reg [63:0] crc;
|
|
reg [63:0] sum;
|
|
|
|
// Take CRC data and apply to testblock inputs
|
|
wire [31:0] in = crc[31:0];
|
|
|
|
/*AUTOWIRE*/
|
|
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
|
wire [31:0] out; // From test of Test.v
|
|
// End of automatics
|
|
|
|
Test test(/*AUTOINST*/
|
|
// Outputs
|
|
.out (out[31:0]),
|
|
// Inputs
|
|
.clk (clk),
|
|
.in (in[31:0]));
|
|
|
|
// Aggregate outputs into a single result vector
|
|
wire [63:0] result = {32'h0, out};
|
|
|
|
// Test loop
|
|
always @ (posedge clk) begin
|
|
`ifdef TEST_VERBOSE
|
|
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
|
|
`endif
|
|
cyc <= cyc + 1;
|
|
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
|
|
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
|
|
if (cyc == 0) begin
|
|
// Setup
|
|
crc <= 64'h5aef0c8d_d70a4497;
|
|
sum <= '0;
|
|
end
|
|
else if (cyc < 10) begin
|
|
sum <= '0;
|
|
end
|
|
else if (cyc < 90) begin
|
|
end
|
|
else if (cyc == 99) begin
|
|
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
|
|
if (crc !== 64'hc77bb9b3784ea091) $stop;
|
|
// What checksum will we end up with (above print should match)
|
|
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
|
|
if (sum !== `EXPECTED_SUM) $stop;
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
module Test(/*AUTOARG*/
|
|
// Outputs
|
|
out,
|
|
// Inputs
|
|
clk, in
|
|
);
|
|
|
|
// Replace this module with the device under test.
|
|
//
|
|
// Change the code in the t module to apply values to the inputs and
|
|
// merge the output values into the result vector.
|
|
|
|
input clk;
|
|
input [31:0] in;
|
|
output reg [31:0] out;
|
|
|
|
always @(posedge clk) begin
|
|
out <= in;
|
|
end
|
|
endmodule
|