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88 lines
2.0 KiB
Verilog
88 lines
2.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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// verilator lint_off GENCLK
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reg printclk;
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// verilator lint_on GENCLK
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ps ps (printclk);
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reg [7:0] a;
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wire [7:0] z;
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l1 u (~a,z);
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always @ (posedge clk) begin
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printclk <= 0;
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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printclk <= 1'b1;
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end
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if (cyc==2) begin
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a <= 8'b1;
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end
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if (cyc==3) begin
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if (z !== 8'hf8) $stop;
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//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
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//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
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//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
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//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
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//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
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//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module ps (input printclk);
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// Check that %m stays correct across inlines
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always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
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endmodule
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module l1 (input [7:0] a, output [7:0] z);
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wire [7:0] z0; wire [7:0] z1;
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assign z = z0+z1;
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l2 u0 (a, z0); l2 u1 (a, z1);
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endmodule
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module l2 (input [7:0] a, output [7:0] z);
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wire [7:0] z0; wire [7:0] z1;
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assign z = z0+z1;
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wire [7:0] a1 = a+8'd1;
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l3 u0 (a, z0); l3 u1 (a1, z1);
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endmodule
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module l3 (input [7:0] a, output [7:0] z);
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wire [7:0] z0; wire [7:0] z1;
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assign z = z0+z1;
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wire [7:0] a1 = a+8'd1;
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l4 u0 (a, z0); l4 u1 (a1, z1);
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endmodule
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module l4 (input [7:0] a, output [7:0] z);
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wire [7:0] z0; wire [7:0] z1;
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assign z = z0+z1;
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wire [7:0] a1 = a+8'd1;
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l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
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endmodule
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module l5 (input [7:0] a, output [7:0] z);
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parameter PARAM = 5;
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wire [7:0] z0; wire [7:0] z1;
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assign z = a;
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endmodule
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