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63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2006 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=0;
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reg [63:0] crc;
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integer i;
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reg [63:0] mem [7:0];
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always @ (posedge clk) begin
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if (cyc==1) begin
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for (i=0; i<8; i=i+1) begin
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mem[i] <= 64'h0;
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end
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end
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else begin
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mem[0] <= crc;
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for (i=1; i<8; i=i+1) begin
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mem[i] <= mem[i-1];
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end
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end
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end
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wire [63:0] outData = mem[7];
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always @ (posedge clk) begin
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//$write("[%0t] cyc==%0d crc=%b q=%x\n",$time, cyc, crc, outData);
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc==90) begin
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if (outData != 64'h1265e3bddcd9bc27) $stop;
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end
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else if (cyc==91) begin
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if (outData != 64'h24cbc77bb9b3784e) $stop;
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end
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else if (cyc==92) begin
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end
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else if (cyc==93) begin
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end
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else if (cyc==94) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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