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19 lines
430 B
Verilog
19 lines
430 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder;
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// SPDX-License-Identifier: CC0-1.0
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module t
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#(parameter WIDTH = 8)
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(/*AUTOARG*/
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// Outputs
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o
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);
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output [WIDTH-1:0] o;
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localparam DEPTH = $clog2(5);
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// Note single bracket below
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reg [WIDTH-1:0] arid [1<<DEPTH];
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assign o = arid[0];
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endmodule
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